A3P250-FG256 SMD / SM TFPGA - Field Programmable Gate Array

Feature

• 15 K to 1 M System Gates

• Up to 144 Kbits of True Dual-Port SRAM

• Up to 300 User I/Os

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Instant On Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

• 350 MHz System Performance

• 3.3 V, 66 MHz 64-Bit PCI†

• ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled ProASIC®3 devices) via JTAG (IEEE 1532–compliant)†

• FlashLock® to Secure FPGA Contents

• Core Voltage for Low Power

• Support for 1.5 V-Only Systems • Low-Impedance Flash Switches• Segmented, Hierarchical Routing and Clock Structure• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V • Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS 2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above) • I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold Sparing I/Os‡

• Programmable Output Slew Rate† and Drive Strength • Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC3 Family

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