LC4064V-75T100C CPLD - Complex Programmable Logic Devices 3.3V 64 I/O

Features:

High Performance
• fMAX = 400 MHz maximum operating frequency
• tPD = 2.5 ns propagation delay
• Up to four global clock pins with programmable
clock polarity control
• Up to 80 PTs per output

Ease of Design
• Enhanced macrocells with individual clock,
reset, preset and clock enable controls
• Up to four global OE controls
• Individual local OE control per I/O pin
• Excellent First-Time-FitTM and refit
• Fast path, SpeedLockingTM Path, and wide-PT
path
• Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders

Zero Power (ispMACH 4000Z) and Low Power (ispMACH 4000V/B/C)
• Typical static current 10 µA (4032Z)
• Typical static current 1.3 mA (4000C)
• 1.8 V core low dynamic power
• ispMACH 4000Z operational down to 1.6 V VCC

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