TPS54232DR Switching Voltage Regulators ADM213EARSZ-REEL BCM88381CA1KFSBG PMIC Power Management ICs

Overview

The TPS54232 is a 28-V, 2-A, step-down (buck) converter with an integrated high-side n-channel MOSFET. To improve performance during line and load transients, the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design. The TPS54232 has a pre-set switching frequency of 1MHz.

The TPS54232 needs a minimum input voltage of 3.5 V to operate normally. The EN pin has an internal pull-up current source that can be used to adjust the input-voltage, undervoltage lockout (UVLO) with two external resistors. In addition, the pull-up current provides a default condition when the EN pin is floating for the device to operate. The operating current is 85 μA typically when not switching and under no load. When the device is disabled, the supply current is 1 μA typically.

The integrated 80-mΩ high-side MOSFET allows for high efficiency power supply designs with continuous output currents up to 2 A.

The TPS54232 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by an external capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the voltage falls below a preset threshold of 2.1 V typically. The output voltage can be stepped down to as low as the reference voltage.

By adding an external capacitor, the slow start time of the TPS54232 can be adjustable which enables flexible output filter selection.

To improve the efficiency at light load conditions, the TPS54232 enters a special pulse-skipping Eco-Mode when the peak inductor current drops below 100 mA typically.

The frequency foldback reduces the switching frequency during startup and over current conditions to help control the inductor current. The thermal shut down gives the additional protection under fault conditions.

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