MC88915TFN70 Phase Locked Loops Wireless RF Integrated Circuits

Features
●Five Outputs (Q0-Q4) with Output-Output Skew < 500 ps each being phase and fequency locked to the SYNC input
●The phase variation from part- to- part betveen the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD
specification, which defines the part-to-part skew)
●Input/ Output phase -locked frequency ratios of 1:2, 1:1, and 2:1 are available
●Input frequency range from 5MHz - 2X _Q FMAX spec. (10MHz - 2X _Q FMAX for the TFN133 version)
●Additional outputs available at 2X and +2 the system“Q" frequency. Also a Q (180° phase shif) output available
●All outputs have +36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs
are TTL-level compatible. +88mA IOL/IOH specifications guarantee 5092 transmission line switching on the incident edge
●Test Mode pin PLL_ EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes.
All outputs can go into high impedance (3-state) for board test purposes
●Lock Indicator (LOCK) accuracy indicates a phase locked state
Yield Surface Modeling and YSM are trademarks of Motorola, Inc.

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